IEC 62530 Ed. 1.0 en:2007

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Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>

Product Details

Edition:

1.0

Published:

11/07/2007

Number of Pages:

663

File Size:

1 file , 6.9 MB