Side Navigation

X

JEDEC JESD 12-3

ADDENDUM No. 3 to JESD12 – CMOS GATE ARRAY MACROCELL STANDARD
Amendment by JEDEC Solid State Technology Association, 06/01/1986

JEDEC JEP001-1A

FOUNDRY PROCESS QUALIFICATION GUIDELINES – BACKEND OF LINE (Wafer Fabrication Manufacturing Sites)
standard by JEDEC Solid State Technology Association, 09/01/2018

JEDEC JESD 36

STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 06/01/1996