JEDEC JESD8-2
ADDENDUM No. 2 to JESD8 – STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 03/01/1993
ADDENDUM No. 2 to JESD8 – STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 03/01/1993
STANDARD FOR CHAIN DESCRIPTION FILE
standard by JEDEC Solid State Technology Association, 06/01/1996
GUIDELINE FOR ASSESSING THE CURRENT-CARRYING CAPABILITY OF THE LEADS IN A POWER PACKAGE SYSTEM
standard by JEDEC Solid State Technology Association, 02/01/2003
GUIDELINE FOR RESIDUAL GAS ANALYSIS (RGA) FOR MICROELECTRONIC PACKAGES
standard by JEDEC Solid State Technology Association, 11/01/2011
TEMPERATURE, BIAS, AND OPERATING LIFE
standard by JEDEC Solid State Technology Association, 11/01/2010
ASSESSMENT OF AVERAGE OUTGOING QUALITY LEVELS IN PARTS PER MILLION (PPM)
standard by JEDEC Solid State Technology Association, 04/01/1995
RECOMMENDED ESD TARGET LEVELS FOR HBM QUALIFICATION
standard by JEDEC Solid State Technology Association, 07/01/2018
SPECIALITY DDR2-1066 SDRAM
standard by JEDEC Solid State Technology Association, 11/01/2007
POD10 – 1.0 V Pseudo Open Drain Interface
standard by JEDEC Solid State Technology Association, 09/01/2011
Graphics Double Data Rate (GDDR6) SGRAM Standard
standard by JEDEC Solid State Technology Association, 07/01/2018