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JEDEC JESD22-C101F

FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC DISCHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS
standard by JEDEC Solid State Technology Association, 10/01/2013

JEDEC JESD 82-12A

DEFINITION OF THE SSTU32S869 & SSTU32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 04/01/2007

JEDEC JEP162

System Level ESD: Part II: Implementation of Effective ESD Robust Designs
standard by JEDEC Solid State Technology Association, 01/01/2013

JEDEC JESD 8-9B

ADDENDUM No. 9B to JESD8 – STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002
standard by JEDEC Solid State Technology Association, 05/01/2002

JEDEC JESD75-1

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE
standard by JEDEC Solid State Technology Association, 10/01/2001

JEDEC JESD82-1A

DEFINITION OF CVF857 PLL CLOCK DRIVER FOR REGISTERED PC1600, PC2100, PC2700, AND PC3200 DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2004