JEDEC JESD 82-12A
DEFINITION OF THE SSTU32S869 & SSTU32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 04/01/2007
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JEDEC JEP162
System Level ESD: Part II: Implementation of Effective ESD Robust Designs
standard by JEDEC Solid State Technology Association, 01/01/2013
JEDEC JESD 8-9B
ADDENDUM No. 9B to JESD8 – STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002
standard by JEDEC Solid State Technology Association, 05/01/2002
JEDEC JESD230D
NAND Flash Interface Interopability
standard by JEDEC Solid State Technology Association, 06/01/2019
JEDEC JESD75-1
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE
standard by JEDEC Solid State Technology Association, 10/01/2001
JEDEC J-STD-609A.01
AND LABELING OF COMPONENTS, PCBs AND PCBAs TO IDENTIFY LEAD (Pb), Pb-FREE AND OTHER ATTRIBUTES
standard by JEDEC Solid State Technology Association, 02/01/2011
JEDEC JESD79-3-3
Addendum No. 1 to 3D Stacked SDRAM
Amendment by JEDEC Solid State Technology Association, 12/01/2013
JEDEC JESD51-31
THERMAL TEST ENVIRONMENT MODIFICATIONS FOR MULTICHIP PACKAGES
standard by JEDEC Solid State Technology Association, 07/01/2008