ADDENDUM No. 11A.01 to JESD8 – 1.5 V +/- 0.1 V (NORMAL RANGE) AND 0.9 – 1.6 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2007
A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS
standard by JEDEC Solid State Technology Association, 12/01/2001
Terms, Definitions, and Letter Symbols for Microelectronic Devices
standard by JEDEC Solid State Technology Association, 12/01/2012
MARKING AND LABELING OF COMPONENTS, PCBs AND PCBAs TO IDENTIFY LEAD (Pb), Pb-FREE AND OTHER ATTRIBUTES
standard by JEDEC Solid State Technology Association, 05/01/2007
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 10/01/2016
TEST METHODS AND ACCEPTANCE PROCEDURES FOR THE EVALUATION OF POLYMERIC MATERIALS
standard by JEDEC Solid State Technology Association, 03/01/2018
Descriptive Designation System for Semiconductor-device Packages
standard by JEDEC Solid State Technology Association, 08/01/2017
USER GUIDELINES FOR IR THERMAL IMAGING DETERMINATION OF DIE TEMPERATURE
standard by JEDEC Solid State Technology Association, 09/01/1999
DEFINITION OF the SSTUA32S869 AND SSTUA32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007
PSO-N/PQFN PINOUTS STANDARDIZED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONS
standard by JEDEC Solid State Technology Association, 03/01/2006