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JEDEC JEP126

GUIDELINE FOR DEVELOPING AND DOCUMENTING PACKAGE ELECTRICAL MODELS DERIVED FROM COMPUTATIONAL ANALYSIS
standard by JEDEC Solid State Technology Association, 05/01/1996

JEDEC JESD8-3A

ADDENDUM No. 3A to JESD8 – GUNNING TRANSCEIVER LOGIC (GTL) LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 05/01/2007

JEDEC JESD82-9B

DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007