JEDEC JEP126
GUIDELINE FOR DEVELOPING AND DOCUMENTING PACKAGE ELECTRICAL MODELS DERIVED FROM COMPUTATIONAL ANALYSIS
standard by JEDEC Solid State Technology Association, 05/01/1996
Side Navigation
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JEDEC JEP137B
COMMON FLASH INTERFACE (CFI) IDENTIFICATION CODES
standard by JEDEC Solid State Technology Association, 05/01/2004
JEDEC JESD8-8
ADDENDUM No. 8 to JESD8 – STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/1996
JEDEC JESD89-3A
TEST METHOD FOR BEAM ACCELERATED SOFT ERROR RATE
standard by JEDEC Solid State Technology Association, 11/01/2007
JEDEC JESD8-3A
ADDENDUM No. 3A to JESD8 – GUNNING TRANSCEIVER LOGIC (GTL) LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 05/01/2007
JEDEC JESD82-9B
DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007
JEDEC JEP104C.01
REFERENCE GUIDE TO LETTER SYMBOLS FOR SEMICONDUCTOR DEVICES
standard by JEDEC Solid State Technology Association, 05/01/2003
JEDEC JESD65B
DEFINITION OF SKEW SPECIFICATIONS FOR STANDARD LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 09/01/2003
JEDEC JESD52
STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 11/01/1995