JEDEC JESD212C
Graphics Double Data Rate (GDDR5) SGRAM Standard
standard by JEDEC Solid State Technology Association, 02/01/2016
Graphics Double Data Rate (GDDR5) SGRAM Standard
standard by JEDEC Solid State Technology Association, 02/01/2016
ELECTRICAL PARAMETERS ASSESSMENT
standard by JEDEC Solid State Technology Association, 10/01/2009
GUIDELINE FOR DEVELOPING AND DOCUMENTING PACKAGE ELECTRICAL MODELS DERIVED FROM COMPUTATIONAL ANALYSIS
standard by JEDEC Solid State Technology Association, 05/01/1996
PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS
standard by JEDEC Solid State Technology Association, 11/01/1973
FLIP CHIP TENSILE PULL
standard by JEDEC Solid State Technology Association, 07/01/2014
TEST METHOD FOR BEAM ACCELERATED SOFT ERROR RATE
standard by JEDEC Solid State Technology Association, 11/01/2007
ADDENDUM No. 3A to JESD8 – GUNNING TRANSCEIVER LOGIC (GTL) LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 05/01/2007
DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007
REFERENCE GUIDE TO LETTER SYMBOLS FOR SEMICONDUCTOR DEVICES
standard by JEDEC Solid State Technology Association, 05/01/2003