JEDEC JESD47J.01
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2017
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2017
COUNTERFEIT ELECTRONIC PARTS: NON-PROLIFERATION FOR MANUFACTURERS
standard by JEDEC Solid State Technology Association, 03/01/2016
EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES
standard by JEDEC Solid State Technology Association, 05/01/2004
FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING
standard by JEDEC Solid State Technology Association, 04/01/2017
RELATIVE SPECTRAL RESPONSE CURVES FOR SEMICONDUCTOR INFRARED DETECTORS
standard by JEDEC Solid State Technology Association, 10/01/1969
CONDITIONS FOR MEASUREMENT OF DIODE STATIC PARAMETERS
standard by JEDEC Solid State Technology Association, 12/01/1992
TEST METHODS AND CHARACTER DESIGNATION FOR LIQUID CRYSTAL DEVICES: Â
standard by JEDEC Solid State Technology Association, 05/01/1982
STANDARD SPECIFICATION FOR DESCRIPTION OF B SERIES CMOS DEVICES
standard by JEDEC Solid State Technology Association, 05/01/1980
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS
standard by JEDEC Solid State Technology Association, 09/01/2004
STANDARD FOR FAILURE ANALYSIS REPORT FORMAT
standard by JEDEC Solid State Technology Association, 12/01/1995