JEDEC JESD60A
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS
standard by JEDEC Solid State Technology Association, 09/01/2004
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS
standard by JEDEC Solid State Technology Association, 09/01/2004
STANDARD FOR FAILURE ANALYSIS REPORT FORMAT
standard by JEDEC Solid State Technology Association, 12/01/1995
SPECIAL REQUIREMENTS FOR MAVERICK PRODUCT ELIMINATION AND OUTLIER MANAGEMENT
standard by JEDEC Solid State Technology Association, 11/01/2008
NAND Flash Interface Interoperability
standard by JEDEC Solid State Technology Association, 10/01/2016
STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS
standard by JEDEC Solid State Technology Association, 08/01/2001
FULLY BUFFERED DIMM DESIGN FOR TEST, DESIGN FOR VALIDATION (DFx)
standard by JEDEC Solid State Technology Association, 07/01/2008
STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 11/01/1999
QUALITY AND RELIABILITY STANDARDS AND PUBLICATIONS
standard by JEDEC Solid State Technology Association, 10/01/1999
DDR4 NVDIMM-N Design Standard
standard by JEDEC Solid State Technology Association, 09/01/2016