JEDEC JESD 24-3
ADDENDUM No. 3 to JESD24 – THERMAL IMPEDANCE MEASUREMENTS FOR VERTICAL POWER MOSFETS (DELTA SOURCE-DRAIN VOLTAGE METHOD)
Amendment by JEDEC Solid State Technology Association, 11/01/1990
ADDENDUM No. 3 to JESD24 – THERMAL IMPEDANCE MEASUREMENTS FOR VERTICAL POWER MOSFETS (DELTA SOURCE-DRAIN VOLTAGE METHOD)
Amendment by JEDEC Solid State Technology Association, 11/01/1990
THE MEASUREMENT OF TRANSISTOR NOISE FIGURE AT FREQUENCIES UP TO 20 kHz BY SINUSOIDAL SIGNAL-GENERATOR METHOD
standard by JEDEC Solid State Technology Association, 04/01/1968
0.6 V Low Voltage Swing Terminated Logic (LVSTL06)
standard by JEDEC Solid State Technology Association, 12/01/2016
RF Biased Life (RFBL) Test Method
standard by JEDEC Solid State Technology Association, 01/01/2013
TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATION
standard by JEDEC Solid State Technology Association, 07/01/1992
REQUIREMENTS FOR HANDLING ELECTROSTATIC-DISCHARGE-SENSITIVE (ESDS) DEVICES
standard by JEDEC Solid State Technology Association, 01/01/2012
STANDARD FOR DESCRIPTION OF 54/74ABTXXX AND 74BCXXX TTL-COMPATIBLE BiCMOS LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 02/01/1996
Universal Flash Storage (UFS)
standard by JEDEC Solid State Technology Association, 06/01/2012
DEFINITION OF THE SSTUB32869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007
FBDIMM Architecture and Protocol
standard by JEDEC Solid State Technology Association, 01/01/2007