JEDEC JESD8-6
ADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/1995
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JEDEC JESD47K
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/2018
JEDEC JESD28-1
N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS
standard by JEDEC Solid State Technology Association, 09/01/2001
JEDEC JESD245
Byte Addressable Energy Backed Interface
standard by JEDEC Solid State Technology Association, 12/01/2015
JEDEC JESD76-3
STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 08/01/2001
JEDEC JESD61A.01
ISOTHERMAL ELECTROMIGRATION TEST PROCEDURE
standard by JEDEC Solid State Technology Association, 10/01/2007
JEDEC JESD89A
MEASUREMENT AND REPORTING OF ALPHA PARTICLE AND TERRESTRIAL COSMIC RAY INDUCED SOFT ERRORS IN SEMICONDUCTOR DEVICES
standard by JEDEC Solid State Technology Association, 10/01/2006
JEDEC JESD77D
Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices
standard by JEDEC Solid State Technology Association, 08/01/2012
JEDEC JESD8-7A
ADDENDUM No. 7 to JESD8 – 1.8 V + -0.15 V (NORMAL RANGE), AND 1.2 V – 1.95 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT
standard by JEDEC Solid State Technology Association, 06/01/2006