ADDENDUM No. 7 to JESD8 – 1.8 V + -0.15 V (NORMAL RANGE), AND 1.2 V – 1.95 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT
standard by JEDEC Solid State Technology Association, 06/01/2006
STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALS
standard by JEDEC Solid State Technology Association, 07/01/2001
INTEGRATED CIRCUITS THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS – NATURAL CONVECTION (STILL AIR)
standard by JEDEC Solid State Technology Association, 01/01/2007
Descriptive Designation System for Semiconductor-device Packages
standard by JEDEC Solid State Technology Association, 01/01/2016
ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing – Human Body Modal (HBM) – Component Level
standard by JEDEC Solid State Technology Association, 05/12/2017
TERMS, DEFINITIONS AND UNITS GLOSSARY FOR LED THERMAL TESTING
standard by JEDEC Solid State Technology Association, 05/01/2012
STANDARD LIST OF VALUES TO BE USED IN SEMICONDUCTOR DEVICE SPECIFICATIONS AND REGISTRATION FORMAT
standard by JEDEC Solid State Technology Association, 10/01/1980
DEFINITION OF EXTERNAL CLEARANCE AND CREEPAGE DISTANCES OF DISCRETE SEMICONDUCTOR PACKAGES FOR THYRISTORS AND RECTIFIER DIODES
standard by JEDEC Solid State Technology Association, 11/01/1983
POD135 – 1.35 V Pseudo Open Drain I/O
standard by JEDEC Solid State Technology Association, 06/01/2019
I/O DRIVERS AND RECEIVERS WITH CONFIGURABLE COMMUNICATION VOLTAGE, IMPEDANCE, AND RECEIVER THRESHOLD
standard by JEDEC Solid State Technology Association, 02/01/1999