JEDEC JESD 47G.01
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 04/01/2010
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 04/01/2010
JOINT IPC/JEDEC STANDARD FOR MOISTURE/REFLOW SENSITIVITY CLASSIFICATION FOR NONHERMETIC SOLID STATE SURFACE-MOUNT DEVICES
standard by JEDEC Solid State Technology Association, 12/01/2014
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES
standard by JEDEC Solid State Technology Association, 11/01/2010
ACCELERATED MOISTURE RESISTANCE – UNBIASED HAST
standard by JEDEC Solid State Technology Association, 07/01/2015
Guide to Standards and Publications Relating to Quality and Reliability of Electronic Hardware
standard by JEDEC Solid State Technology Association, 10/01/2013
REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION
standard by JEDEC Solid State Technology Association, 10/01/2006
METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESS
standard by JEDEC Solid State Technology Association, 03/01/2006
HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST)
standard by JEDEC Solid State Technology Association, 11/01/2010
Low Power Double Data Rate 3 SDRAM (LPDDR3)
standard by JEDEC Solid State Technology Association, 08/01/2015
MARKING, SYMBOLS, AND LABELS OF LEADED AND LEAD-FREE TERMINAL FINISHED MATERIALS USED IN ELECTRONIC ASSEMBLY
standard by JEDEC Solid State Technology Association, 04/01/2016