JEDEC JESD67
I/O DRIVERS AND RECEIVERS WITH CONFIGURABLE COMMUNICATION VOLTAGE, IMPEDANCE, AND RECEIVER THRESHOLD
standard by JEDEC Solid State Technology Association, 02/01/1999
Side Navigation
X
JEDEC JESD94A
APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGY
standard by JEDEC Solid State Technology Association, 07/01/2008
JEDEC JESD76
DESCRIPTION OF 1.8 V CMOS LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 04/01/2000
JEDEC JESD75-2
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16-BIT LOGIC FUNCTIONS
standard by JEDEC Solid State Technology Association, 07/01/2001
JEDEC JESD8-33
.05 Low Voltage Swing Terminated Logic (LVSTL05)
standard by JEDEC Solid State Technology Association, 06/01/2019
JEDEC JESD82-4B
STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2003
JEDEC JESD82-7A
DEFINITION OF THE SSTU32864 1.8-V CONFIGURABLE REGISTERED BUFFER FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 10/01/2004
JEDEC JESD73
DESCRIPTION OF 5 V BUS SWITCH WITH TTL-COMPATIBLE CONTROL INPUTS
standard by JEDEC Solid State Technology Association, 06/01/1999
JEDEC JESD82-31
DDR4 REGISTER CLOCK DRIVER (DDR4RCD01)
standard by JEDEC Solid State Technology Association, 08/01/2016
JEDEC JESD89-2A
TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE
standard by JEDEC Solid State Technology Association, 10/01/2007