JEDEC JESD403-1A
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages.
Product Details
- Published:
- 12/01/2021
- Number of Pages:
- 60
- File Size:
- 1 file , 1.7 MB
- Note:
- This product is unavailable in Belarus, Russia, Ukraine